Generally, the speed at which an integrated circuit operates is influenced by the distance between the farthest separated components that communicate with each other on the chip. Laying out circuits as three-dimensional structures has been shown to significantly reduce the communication path length between on-chip components, provided the vertical distances between the layers are much smaller than the chip width of the individual layers. Thus, by stacking circuit layers vertically, the overall chip speed is typically increased. One method that has been used to implement such stacking is through wafer bonding. Wafer bonding is the joining together of two or more semiconductor wafers on which integrated circuitry has been formed. Wafers are typically joined by direct bonding of external oxide layers or by adding adhesives to inter-level dielectric (ILD) layers. The bonded result produces a three-dimensional wafer stack that is subsequently diced into separate “stacked die,” with each individual stacked die having multiple layers of integrated circuitry. In addition to the increased speed that the three-dimensional circuitry typically experiences, wafer stacking offers other potential benefits, including improved form factors, lower costs, and greater integration through system on chip solutions. In order to enable the various components integrated within each stacked die, electrical connections are provided that provide conductors between vertical layers.
Vias have been routinely used in semiconductor fabrication to provide electrical coupling between one or more layers of conductive material within a semiconductor device. More recently, through-silicon vias (TSVs) have arisen as a method of overcoming limitations of conventional wire bonding for example, as increases in performance and density requirements no longer allow traditional wire bonding to be adequate. TSVs allow for shorter interconnects by forming an interconnect in the z-axis. The interconnect is created through a substrate (e.g. wafer), by forming a via extending from a front surface to a back surface of the substrate. TSVs are also useful in forming interconnects for stacked wafers, stacked die, and/or combinations thereof.
The use of TSVs technology however creates challenges. The aspect ratio of the via may be quite high (e.g. the thickness of the substrate or the depth of the via is large as compared to the diameter of the via). Conventional methods of forming a via may lead to an undesirable undercut in layers (e.g. undercuts between dielectric hard mask and silicon) of the substrate. In one approach for eliminating the silicon undercut profile, a sacrificial polymer is formed on the vertical surfaces of the hard mask opening to protect a dielectric hard mask from lateral etching in subsequent via etching process. Such a pre-treatment leads to a new set of problems and issues associated with via filling process. For example, issues include a silicon birds beak profile existed at the silicon edge and a roughness sidewall (e.g., a scalloping pattern on the top of the via sidewall), which cause poor sidewall coverage, improper formation in depositing a seed layer, a barrier layer and/or a passivation layer processes, and become an obstacle to accelerating the via filling process. The sidewall scalloping roughness also has an impact on TSV electrical performance.
Accordingly, there is a need for an improved via and a method of fabricating such to avoid the shortcomings of the conventional process.